Location: Budapest, Hungary
RTL Development Engineer trainee
We are looking for enthusiastic students for the RTL design engineering
position in our Budapest office. The task is part-time hardware development in
SystemVerilog language.
By accepting our offer, you'll have the opportunity to
Understand the digital ASIC design process through real industry related
tasks
Master the steps for optimal RTL code design for both ASIC and FPGA
platforms
Participate in the implementation of neural networks
Gain implementation practice in high performance computing
Gain proficiency in the optimization of power consumption and clock signal
frequency of completed RTL specifications
Gain experience in designing for a safety-critical application area
(self-driving car / satellite)
Responsibilities
Participation in research and development of a neural network accelerator
chip
Implementation of functional units in SystemVerilog language
We provide the test environment for your module
Key Qualifications
Ongoing university studies
Flexibility, effective and efficient teamwork
Reliable and quality oriented attitude
What We Offer
Possibility to gain valuable work experience at the forefront of the RTL
Design development sector
Competitive student salary and long-term bonus system
Inspiring and supportive working environment
Teambuilding events and other benefits for students
Flexible working hours
Long-term job opportunity
Possibility of an immediate start
In-service training opportunity
Fitness opportunities
Free lunch every workday, nearby at one of the best all-you-can-eat
restaurants in Budapest or delivered by Wolt for Work
